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1 ltc1414 14-bit, 2.2msps, sampling a/d converter effective bits and signal-to-noise + distortion vs input frequency 14-bit adc 14 5v optional 3v logic supply 10 m f av dd dv dd ov dd ognd 1414 ta01 dgnd d13 (msb) d0 (lsb) busy s/h buffer ltc1414 4.0625v 2k ?v 2.5v reference timing and logic output buffers convst agnd v ss 10 m f 10 m f v ref comp a in a in + 1 m f input frequency (hz) effective bits s/(n + d) (db) 10k 100k 1m 10m 1414 ta02 1k 14 13 12 11 10 9 8 7 6 5 4 3 2 86 80 74 68 f sample = 2.2mhz typical applicatio u the ltc ? 1414 is a 14-bit, 2.2msps, sampling a/d con- verter which draws only 175mw from 5v supplies. this high performance adc includes a high dynamic range sample-and-hold, a precision reference and requires no external components. the ltc1414s high performance sample-and-hold has a full-scale input range of 2.5v. outstanding ac perfor- mance includes 80db s/(n + d) and 95db sfdr with a 100khz input. the performance remains high at the nyquist input frequency of 1.1mhz with 78db s/(n + d) and 84db sfdr. the unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 40mhz bandwidth. the 70db common mode rejection can elimi- nate ground loops and common mode noise by measuring signal differentially from the source the adc has a microprocessor compatible, 14-bit parallel output port. there is no pipline delay in the conversion results. n sample rate: 2.2msps n outstanding spectral purity: 80db s/(n + d) and 95db sfdr at 100khz 78db s/(n + d) and 84db sfdr at nyquist n ultralow distortion with single-ended or differential inputs n 2.5v bipolar input range eliminates level shifting and rail-to-rail op amp requirements n easy hookup for external or internal reference n no pipeline delay n power dissipation: 175mw on 5v supplies n 28-pin narrow ssop package , ltc and lt are registered trademarks of linear technology corporation. features descriptio u n telecommunications n digital signal processing n multiplexed data acquisition systems n high speed data acquisition n spectrum analysis n imaging systems applicatio s u
2 ltc1414 absolute m axi m u m ratings w ww u package/order i n for m atio n w u u av dd = ov dd = dv dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................. 6v negative supply voltage (v ss ) ................................ C 6v total supply voltage (v dd to v ss ) .......................... 12v analog input voltage (note 3) ......................... (v ss C 0.3v) to (v dd + 0.3v) digital input voltage (note 4) .......... (v ss C 0.3v) to 10v digital output voltage ........ (v ss C 0.3v) to (v dd + 0.3v) power dissipation .............................................. 500mw operating temperature range ltc1414c ............................................... 0 c to 70 c ltc1414i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 110 c, q ja = 110 c/ w consult factory for industrial, military and a grade parts. ltc1414cgn ltc1414ign symbol parameter conditions min typ max units v in analog input range 4.75v v dd 5.25v, C 5.25v v ss C 4.75v l 2.5 v i in analog input leakage current between conversions l 1 m a c in analog input capacitance between conversions 8 pf during conversions 4 pf t acq sample-and-hold acquisition time l 40 100 ns t ap sample-and-hold aperture delay time C 1 ns t jitter sample-and-hold aperture delay time jitter 3 ps rms cmrr analog input common mode rejection ratio C 2.5v < (a in C = a in + ) < 2.5v 70 db (notes 5, 6) cc hara terist ics co u verter ltc1414 parameter conditions min typ max units resolution (no missing codes) l 13 bits integral linearity error (note 7) l 0.75 2.0 lsb differential linearity error l 0.75 1.75 lsb offset error (note 8) 5 20 lsb l 24 lsb full-scale error internal reference 10 60 lsb external reference = 2.5v 5 25 lsb full-scale tempco internal reference 15 ppm/ c external reference = 2.5v 1 ppm/ c put u i a a u log (note 5) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a in + a in v ref refcomp agnd d13 (msb) d12 d11 d10 d9 d8 d7 d6 ognd av dd agnd v ss busy convst dgnd dv dd ov dd d0 d1 d2 d3 d4 d5
3 ltc1414 (note 5) symbol parameter conditions min typ max units s/(n + d) signal-to-noise plus distortion ratio 100khz input signal 80 db 1.1mhz input signal 78 db thd total harmonic distortion 100khz input signal, first 5 harmonics C 95 db 1.1mhz input signal, first 5 harmonics C 83 db sfdr spurious free dynamic range 100khz input signal, first 5 harmonics 95 db 1.1mhz input signal, first 5 harmonics 84 db imd intermodulation distortion f in1 = 29.37khz, f in2 = 32.446khz C 86 db full power bandwidth 40 mhz full linear bandwidth s/(n + d) 3 74db 3 mhz accuracy ic dy u w a (note 5) i ter al refere ce characteristics u uu parameter conditions min typ max units v ref output voltage i out = 0 2.480 2.500 2.520 v v ref output tempco i out = 0 15 ppm/ c v ref line regulation 4.75v v dd 5.25v 0.01 lsb/ v C 5.25v v ss C 4.75v 0.01 lsb/ v v ref output resistance ? i out ? 0.1ma 2 k w comp output voltage i out = 0 4.06 v (note 5) digital i puts a n d outputs u u symbol parameter conditions min typ max units v dd positive supply voltage (note 9) 4.75 5.25 v v ss negative supply voltage (note 9) C 4.75 C 5.25 v i dd positive supply current cs high l 12 16 ma i ss negative supply current cs high l 23 30 ma p d power dissipation 175 230 mw power require e ts w u (note 5) symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance 1.2 pf v oh high level output voltage v dd = 4.75v, i o = C 10 m a 4.74 v v dd = 4.75v, i o = C 200 m a l 4.0 v v ol low level output voltage v dd = 4.75v, i o = 160 m a 0.05 v v dd = 4.75v, i o = 1.6ma l 0.10 0.4 v i source output source current v out = 0v C 10 ma i sink output sink current v out = v dd 10 ma
4 ltc1414 ti i g characteristics w u (note 5) symbol parameter conditions min typ max units f sample(max) maximum sampling frequency l 2.2 mhz t conv conversion time l 220 330 400 ns t acq acquisition time l 40 100 ns t throughput throughput time (acquisition + conversion) l 370 454 ns t 1 convst to busy delay c l = 25pf 10 ns t 2 data ready before busy - 20 ns t 3 delay between conversions (note 9) l 100 ns t 4 convst low time (note 10) l 40 ns t 5 convst high time (note 10) l 40 ns t 6 aperture delay of sample-and-hold C 1 ns the l denotes specifications which apply over the full operating temperature range; all other limits and typicals t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd and agnd wired together (unless otherwise noted). note 3: when these pin voltages are taken below v ss or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss or above v dd without latchup. note 4: when these pin voltages are taken below v ss , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, v ss = C 5v, f sample = 2.2mhz and t r = t f = 5ns unless otherwise specified. note 6: linearity, offset and full-scale specifications apply for a single- ended a in + input with a in C grounded. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from C 0.5lsb when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. note 9: recommended operating conditions. note 10: the falling convst edge starts a conversion. if convst returns high at a critical point during the conversion it can create small errors. for best results ensure that convst returns high either within 225ns after the start of the conversion or after busy rises. typical perfor a ce characteristics uw signal-to-noise ratio vs input frequency input frequency (hz) 10k signal-to-noise ratio (db) 90 80 70 60 50 40 30 20 10 0 100k 1m 10m 1414 g02 input frequency (hz) 10k distortion (db) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 100k 1m 10m 1414 g03 2nd thd 3rd input frequency (hz) effective bits s/(n + d) (db) 10k 100k 1m 10m 1414 ta02 1k 14 13 12 11 10 9 8 7 6 5 4 3 2 86 80 74 68 f sample = 2.2mhz s/(n + d) vs input frequency distortion vs input frequency
5 ltc1414 typical perfor a ce characteristics uw pi n fu n ctio n s uuu a in + (pin 1): positive analog input. 2.5v input range when a in C is grounded. 2.5v differential if a in C is driven differentially with a in + . a in C (pin 2): negative analog input. can be grounded or driven differentially with a in + . v ref (pin 3): 2.5v reference output. refcomp (pin 4): 4.06v reference bypass pin. bypass to agnd with 10 m f ceramic or 10 m f tantalum in parallel with 0.1 m f ceramic. agnd (pin 5): analog ground. d13 to d6 (pins 6 to 13): data outputs. ognd (pin 14): digital ground for the output drivers. tie to agnd d5 to d0 (pins 15 to 20): data outputs. ov dd (pin 21): positive supply for the output drivers. tie to pin 28 when driving 5v logic. for 3v logic, tie to supply of the logic being driven. dv dd (pin 22): 5v positive supply. tie to pin 28. dgnd (pin 23): digital ground. tie to agnd. convst (pin 24): conversion start signal. this active low signal starts a conversion on its falling edge. spurious-free dynamic range vs input frequency intermodulation distortion plot differential nonlinearity vs output code input frequency (hz) 10k spurious-free dynamic range (db) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 100k 1m 10m 1414 g04 output code 0 4096 8192 12288 16384 dnl (lsbs) 1414 g06 2.0 1.0 0 1.0 2.0 integral nonlinearity vs output code power supply feedthrough vs ripple frequency input common mode rejection vs input frequency input frequency (hz) 1k common mode rejection (db) 80 70 60 50 40 30 20 10 0 10k 100k ltc1414 ?f12 1m 10m output code 0 4096 8192 12288 16384 inl (lsbs) 1414 g07 2.0 1.0 0 1.0 2.0 frequency (khz) 0 400 800 200 600 1000 amplitude (db) 1414 f05a 0 ?0 ?0 ?0 ?0 100 120 f sample = 2.2mhz f in1 = 80.566khz f in2 = 97.753khz ripple frequency (hz) 0 2m4m6m8m10m amplitude of power supply feedthrough (db) 1414 g08 0 ?0 ?0 ?0 ?0 100 120 v ss (v ripple = 0.02v) v dd (v ripple = 0.2v) ognd (v ripple = 0.5v) ov dd (v ripple = 0.5v)
6 ltc1414 pi n fu n ctio n s uuu busy (pin 25): the busy output shows the converter status. it is low when a conversion is in progress. v ss (pin 26): C 5v negative supply. bypass to agnd with 10 m f ceramic or 10 m f tantalum in parallel with 0.1 m f ceramic. agnd (pin 27): analog ground. av dd (pin 28): 5v positive supply. bypass to agnd with 10 m f ceramic or 10 m f tantalum in parallel with 0.1 m f ceramic. fu n ctio n al block diagra uu w 14-bit capacitive dac comp ref amp 2.5v ref 2k refcomp (4.06v) c sample c sample d13 d0 busy control logic internal clock convst zeroing switches ov dd ognd av dd dv dd v ss a in + a in v ref agnd dgnd 14 1414 bd + successive approximation register output latches ti i g diagra u ww data (n ?1) db13 to db0 convst busy 1414 td t 4 t 5 t conv t 1 t 3 t 2 data n db13 to db0 data (n + 1) db13 to db0 data
7 ltc1414 applicatio n s i n for m atio n wu u u conversion details the ltc1414 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel output. the adc is complete with a precision reference and an internal clock. the device is easy to interface with microprocessors and dsps. (please refer to the digital interface section for the data format.) conversion start is controlled by the convst input. at the start of the conversion the successive approximation register (sar) is reset. once a conversion cycle has begun it cannot be restarted. during the conversion, the internal differential 14-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the a in + and a in C inputs are connected to the sample-and-hold capacitors (c sample ) during the acquire phase, and the comparator offset is nulled by the zeroing switches. in this acquire phase, a minimum delay of 70ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. during the convert phase the comparator zeroing switches open, putting the comparator into compare mode. the input switches connect the c sample capacitors to ground, transferring the differential analog input charge onto the summing junction. this input charge is successively com- pared with the binary-weighted charges supplied by the differential capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the differential dac output balances the a in + and a in C input charges. the sar contents (a 14-bit data word) which represents the difference of a in + and a in C are loaded into the 14-bit output latches. dynamic performance the ltc1414 has excellent high speed sampling capabil- ity. fft (fast four transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algo- rithm, the adcs spectral content can be examined for frequencies outside the fundamental. figure 2 shows a typical ltc1414 fft plot. 1414 f01 output latch sar c dac + c dac v dac v dac + + comp d13 d0 14 hold hold hold a in + a in zeroing switches c sample c sample + hold sample sample figure 1. simplified block diagram signal-to-noise ratio the signal-to-(noise + distortion) ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 2a shows a typical spectral content with a 2.2mhz sampling rate and a 100khz input. the dynamic performance is excellent for input frequencies up to and beyond the nyquist limit of 1.1mhz. (see figure 2b) figure 2a. ltc1414 nonaveraged, 2048 point fft, input frequency = 100khz frequency (khz) 0 400 800 200 600 1000 amplitude (db) 1414 f02a 0 ?0 ?0 ?0 ?0 100 120 sinad = 80db sfdr = 96db f sample = 2.2mhz f in = 97.753khz
8 ltc1414 applicatio n s i n for m atio n wu u u frequency (khz) 0 400 800 200 600 1000 amplitude (db) 1414 f02b 0 ?0 ?0 ?0 ?0 100 120 sinad = 78db sfdr = 84db f sample = 2.2mhz f in = 997.949khz intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to the thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies f a and f b are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mf a nf b , where m and n = 0, 1, 2, 3 etc. for example, the 2nd order imd terms include (f a f b ). if the two input sine waves are equal in magnitude, the value (in db) of the 2nd order imd products can be expressed by the following formula: figure 3. effective bits and signal/(noise + distortion) vs input frequency input frequency (hz) effective bits s/(n + d) (db) 10k 100k 1m 10m 1414 ta02 1k 14 13 12 11 10 9 8 7 6 5 4 3 2 86 80 74 68 f sample = 2.2mhz figure 4. distortion vs input frequency effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: enob s = [s/(n + d) C 1.76]/6.02 where s/(n + d) is expressed in db. at the maximum sampling rate of 2.2mhz the ltc1414 maintains near ideal enobs up to the nyquist input frequency of 1.1mhz. refer to figure 3. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd vvv v v n = +++? 20 2 2 3 2 4 22 1 log where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. thd vs input frequency is shown in figure 4. the ltc1414 has good distortion performance up to the nyquist frequency and beyond. figure 2b. ltc1414 2048 point fft, input frequency = 1mhz input frequency (hz) distortion (db) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 1 100k 1m 10m 1414 f04 10k 3rd thd 2nd
9 ltc1414 applicatio n s i n for m atio n wu u u imd f f amplitude at f f amplitude at f ab ab a () = () ? ? 20log the full-linear bandwidth is the input frequency at which the s/(n + d) has dropped to 74db (12 effective bits). the ltc1414 has been designed to optimize input bandwidth, allowing the adc to undersample input signals with fre- quencies above the converters nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) becomes dominated by distortion at frequencies far be- yond nyquist. driving the analog input the differential analog inputs of the ltc1414 are easy to drive. the inputs may be driven differentially or as a single- ended input (i.e., the a in C input is grounded). the a in + and a in C inputs are sampled at the same instant. any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample- and-hold circuit. the inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. during conversion, the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low then the ltc1414 inputs can be driven directly. as source impedance increases so will acquisition time (see figure 6). for minimum acquisition time, with high source impedance, a buffer amplifier should be used. the only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 70ns for full throughput rate). peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in db relative to the rms value of a full- scale input signal. full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is re- duced by 3db for a full-scale input signal. frequency (khz) 0 400 800 200 600 1000 amplitude (db) 1414 f05a 0 ?0 ?0 ?0 ?0 100 120 f sample = 2.2mhz f in1 = 80.566khz f in2 = 97.753khz frequency (khz) 0 400 800 200 600 1000 amplitude (db) 1414 f05b 0 ?0 ?0 ?0 ?0 100 120 f sample = 2.2mhz f in1 = 970.019khz f in2 = 1.492mhz figure 6. acquisition time vs source resistance source resistance ( w ) 10 0.01 acquisition time ( m s) 0.1 1 10 100 1k 1414 fo6 10k 100k figure 5a. intermodulation distortion plot with inputs at 80khz and 97khz figure 5b. intermodulation distortion plot with input signals of 1mhz and 1.5mhz
10 ltc1414 applicatio n s i n for m atio n wu u u choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100 w ) at the closed-loop bandwidth frequency. for example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50mhz, then the output impedance at 50mhz must be less than 100 w . the second requirement is that the closed-loop bandwidth must be greater than 40mhz to ensure adequate small- signal settling for full throughput rate. if slower op amps are used, more settling time can be provided by increasing the time between conversions. the best choice for an op amp to drive the ltc1414 will depend on the application. generally applications fall into two categories: ac applications where dynamic specifica- tions are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the ltc1414. more detailed information is available in the linear technology databooks and on the linearview tm cd-rom. lt ? 1223: 100mhz video current feedback amplifier. 6ma supply current. 5v to 15v supplies. low noise. good for ac applications. lt1227: 140mhz video current feedback amplifier. 10ma supply current. 5v to 15v supplies. low noise. best for ac applications. lt1229/lt1230: dual and quad 100mhz current feed- back amplifiers. 2v to 15v supplies. low noise. good ac specifications, 6ma supply current each amplifier. lt1360: 50mhz voltage feedback amplifier. 3.8ma sup- ply current. good ac and dc specs. 5v to 15v supplies. 70ns settling to 0.5lsb. lt1363: 70mhz, 1000v/ m s op amps. 6.3ma supply cur- rent. good ac and dc specifications. 60ns settling to 0.5lsb. lt1364/lt1365: dual and quad 70mhz, 1000v/ m s op amps. 6.3ma supply current per amplifier. 60ns settling to 0.5lsb. linearview is a trademark of linear technology corporation. ac coupled inputs in applications where only the ac component of the analog input is important, it may be desirable to ac couple the input. this is easily accomplished by dc biasing the ltc1414 analog input with a resistor to ground and using a coupling capacitor to the input. figure 7 shows a simple ac coupled input circuit for the ltc1414 using only two additional components. c1 is a 10 m f ceramic capacitor and r1 is a 1000 w resistor to ground. r1 and c1 form a highpass filter with a lower cut off frequency of 1/2 p (c1)r1 or 15.9hz. differential drive in some applications the adc drive circuitry is differential. the differential drive can be applied directly to the ltc1414 without any special translation circuitry. differential drive can be advantageous at high frequencies (>1mhz) since it provides improved thd and sfdr. transformers can be used to provide ac coupling, input scaling and single ended to differential conversion as shown in figure 8. the resistor r s across the secondary will determine the input impedance on the primary. the input impedance of the primary r p will be related to the secondary load resistor r s by the equation r p = r s /n 2 for example, if a minicircuits t4-6t transformer is used, the turns ratio is 2; if r s is 200 w then r p is equal to 50 w . the center tap of the secondary will set the common mode voltage and should be grounded for optimal ac performance. ltc1414 a in + analog input a in v ref refcomp agnd ltc1414 ?f07 1 2 3 4 5 r1 1k c1 10 f 10 f 1 f figure 7. ac coupled input
11 ltc1414 applicatio n s i n for m atio n wu u u input range the 2.5v input range of the ltc1414 is optimized for low noise and low distortion. most op amps also perform best over this same range, allowing direct coupling to the analog inputs and eliminating the need for special transla- tion circuitry. some applications may require other input ranges. the ltc1414 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. the following sections describe the reference and input circuitry and how they affect the input range. internal reference the ltc1414 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500v. it is connected internally to a reference amplifier and is available at v ref (pin 3), see figure 10. a 2k resistor is in series with the output so that it can be easily overdriven by an external reference or other cir- cuitry. the reference amplifier multiplies the voltage at the v ref pin by 1.625 to create the required internal reference voltage. this provides buffering between the v ref pin and the high speed capacitive dac. the reference amplifier compensation pin, refcomp (pin 4) must be bypassed with a capacitor to ground. the reference amplifier is stable with capacitors of 1 m f or greater. for the best noise performance, a 10 m f ceramic or 10 m f tantalum in parallel with a 0.1 m f ceramic is recommended. figure 8. if a transformer coupled input is required, this circuit provides a simple solution ltc1414 a in + input a in v ref refcomp agnd ltc1414 ?f09 1 2 3 4 5 500pf 100 10 m f figure 9. an rc filter reduces the adcs 40mhz bandwidth to 3.2mhz and filters out wideband noise which may be present in the input signal input filtering the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the ltc1414 noise and distortion. the small-signal band- width of the sample-and-hold circuit is 40mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. for example, figure 9 shows a 500pf capacitor from a in + to ground and a 100 w source resistor to limit the input bandwidth to 3.2mhz. the 500pf capacitor also acts as a charge reservoir for the input sample-and-hold and iso- lates the adc input from sampling glitch-sensitive cir- cuitry. high quality capacitors and resistors should be used since poor quality components can add distortion. npo and silver mica type dielectric capacitors have excel- lent linearity. carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. figure 10. ltc1414 reference circuit r2 40k r3 64k reference amp 10 f refcomp agnd v ref r1 2k 3 4 5 2.500v 4.0625v ltc1414 1414 f10 + bandgap reference ltc1414 a in + analog input a in v ref refcomp agnd ltc1414 ?f08 1 2 3 4 5 r1 50 10 f 1 f r2 50 c1 500pf r s 1:n r p
12 ltc1414 applicatio n s i n for m atio n wu u u the v ref pin can be driven with a dac or other means shown in figure 11. this is useful in applications where the peak input signal amplitude may vary. the input span of the adc can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. the filtering of the internal ltc1414 reference amplifier will limit the bandwidth and settling time of this circuit. a settling time of 5ms should be allowed after a reference adjustment. the output is twos complement binary with 1lsb = fs C (C fs)/16384 = 5v/16384 = 305.2 m v. in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. figure 14 shows the extra components required for full-scale error adjustment. zero offset is achieved by adjusting the offset applied to the a in C input. for zero offset error apply C 152 m v (i.e., C 0.5lsb) at a in + and adjust the offset at the a in C input until the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. for full-scale adjustment, an input voltage of 2.499544v (fs C 1.5lsbs) is applied to a in + and r2 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11. figure 11. driving v ref with a dac ltc1414 a in + analog input 2v to 3v differential a in v ref refcomp agnd 1414 f11 1 2 3 4 5 10 m f ltc1450 2v to 3v differential inputs the ltc1414 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. the adc will always convert the difference of a in + C ( a in C ) independent of the common mode voltage. the common mode rejection holds up to extremely high frequencies, see figure 12. the only requirement is that neither input can exceed the av dd or av ss power supply voltages. integral nonlinearity er- rors (inl) and differential nonlinearity errors (dnl) are independent of the common mode voltage, however, the bipolar zero error (bze) will vary. the change in bze is typically less than 0.1% of the common mode voltage. dynamic performance is also affected by the common mode voltage. thd will degrade as the inputs approach either power supply rail, from C84db with a common mode of 0v to C75db with a common mode of 2.5v or C2.5v. full-scale and offset adjustment figure 13 shows the ideal input/output characteristics for the ltc1414. the code transitions occur midway between successive integer lsb values (i.e., C fs + 0.5lsb, C fs + 1.5lsb, C fs + 2.5lsb,...fs C 2.5lsb, fs C 1.5lsb). figure 12. cmrr vs input frequency input frequency (hz) 1k common mode rejection (db) 80 70 60 50 40 30 20 10 0 10k 100k ltc1414 ?f12 1m 10m figure 13. ltc1414 transfer characteristics input range output code ltc1414 ?f13 011?11 011?10 011?01 000?00 111?11 100?00 100?01 100?10 fs ?1lsb 0 ?fs ?1lsb)
13 ltc1414 applicatio n s i n for m atio n wu u u figure 14. offset and full-scale adjust circuit ltc1414 a in + analog input a in v ref refcomp agnd ltc1414 ?f14 1 2 3 r4 100 w r2 50k r3 24k ?v r6 24k r1 50k r5 47k 4 5 10 m f board layout and bypassing to obtain the best performance from the ltc1414, a printed circuit board with a ground plane is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital line alongside an analog signal line or underneath the adc. the analog input should be screened by agnd. high quality tantalum and ceramic bypass capacitors should be used at the v dd , v ss and v ref pins. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc1414 has differential inputs to minimize noise coupling. common mode noise on the a in + and a in C inputs will be reflected by the input cmrr. the a in C input can be used as a ground sense for the a in + input; the ltc1414 will hold and convert the difference voltage between a in + and a in C . the leads to a in + (pin 1) and a in C (pin 2) should be kept as short as possible. in applications where this is not possible, the a in + and a in C traces should be run side by side to equalize coupling. a single point analog ground separate from the logic system ground should be established with an analog ground plane at agnd (pin 5, 27) or as close as possible to the adc (see figure 8). the adcs dgnd (pin 23) and all other analog grounds should be connected to this single analog ground point. no other digital grounds should be connected to this analog ground point. low impedance analog and digital power supply common returns are essential to low noise operation of the adc and these traces should be as wide as possible. excessive capacitive loading on the adcs data output lines can generate large transient currents on the adc supplies which may affect conversion results. in these cases, the use of digital buffers is recommended to isolate the adc from the excessive loading. example layout figures 16a, 16b, 16c and 16d show the schematic and layout of an evaluation board. the layout demonstrates the proper use of decoupling capacitors and ground plane with a two layer printed circuit board. 1414 f15 a in + agnd refcomp v ss av dd ltc1414 digital system analog input circuitry 5, 27 4 2 26 28 ov dd 21 ognd dgnd 14 23 1 10 m f a in 10 m f 10 m f dv dd 22 analog ground plane + figure 15. power supply grounding practice
14 ltc1414 applicatio n s i n for m atio n wu u u figure 16a. evaluation circuit schematic u4 ltc1414cgn b[00:13] u5 74hc574 u6 74hc574 13 12 u7f, hc14 98 u7d, hc14 j6-13 j6-14 j6-11 j6-12 j6-9 j6-10 j6-7 j6-8 j6-5 j6-6 j6-3 j6-4 j6-1 j6-2 j6-15 j6-16 j6-17 j6-18 d13 d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d13 rdy d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d13 rdy dgnd dgnd d[00:13] header 18-pin 11 10 u7e, hc14 r21 1k d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d07 d06 d09 d10 d11 d12 d13 d00 d01 d02 d03 d04 d05 d08 b00 b01 b02 b03 b04 b05 b08 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 12 q0 q1 q2 q3 q4 q5 q6 q7 q0 q1 q2 q3 q4 q5 q6 q7 0e 0e data ready v ss c5 1 f 10v c6 15pf c15 1 f 10v 1 2 3 4 25 24 23 22 21 28 26 27 5 14 6 7 8 9 10 11 12 13 15 16 17 18 19 20 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 b07 b06 b09 b10 b11 b12 b13 1 11 2 3 4 5 6 7 8 9 1 11 2 3 4 5 6 7 8 9 (msb)d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a in + a in v ref refcomp busy convst dgnd ov dd ov dd av dd v ss agnd agnd ognd v cc v ref v out c9 1 f 10v c8 1 f 10v c11 470pf c13 4.7 f 10v 1414 f16a u1 lt1363 dip-8 (optional) 2 3 4 7 v v + 6 8 1 v logic gnd dgnd pwr 7 14 u7g, hc14 + u3 lt1363 so-8 2 3 4 7 v v + 6 8 1 + c3 0.1 f v ss v cc v cc c4 0.1 f r15 51 r17 10k r18 10k r16 51 jp3 jp2 jp4 j5 a j4 a + j9 r19 51 j7 clk j8 j10 j2 gnd d2 ss12 c2 22 f 10v agnd dgnd j3 5v dgnd + v ss d1 ss12 c2 22 f 10v j1 ?v + v cc dgnd c10 10 f 10v c14 0.1 f v logic + r14 20 0.125w c12 0.1 f c7 0.1 f notes: unless otherwise specified 1. all resistor values in ohms, 1/10w, 5% 2. all capacitor values in f, 25v, 20% and in pf, 50v, 10%
15 ltc1414 applicatio n s i n for m atio n wu u u figure 16b. evaluation circuit board component side silkscreen
16 ltc1414 applicatio n s i n for m atio n wu u u figure 16c. evaluation circuit board component side layout
17 ltc1414 applicatio n s i n for m atio n wu u u figure 16d. evaluation circuit board solder side layout
18 ltc1414 digital interface the a/d converter has just one control input convst. data is output on 14-bit parallel bus. an additional output busy indicates the converter status. digital outputs the parallel digital outputs of the ltc1414 are designed to interface to ttl and cmos logic. the output data is twos complement coded. the output drivers have a separate power pin (ov dd ) and ground pin (ognd). this allows relatively noisy output ground and the output supply bypass ground to be sepa- rated from the other adc grounds. additionally, the ov dd pin may be driven by the supply of the logic that is being driven. for example, the ov dd supply may be 3v while ltc1414 dv dd and av dd pins are 5v, allowing 3v logic to be driven directly. care should be taken to not load the digital outputs with excessive capacitance. large capacitive loads result in large charging currents which can cause conversion er- rors. it is recommended that the capacitive loading is kept under 20pf. if it is not possible to keep the capacitance low, a buffer or latch may be used to isolate the ltc1414 from the capacitive load. timing and control the conversion start is controlled by the convst input. the falling edge of convst will start a conversion. once initiated, it cannot be restarted until the conversion is complete. converter status is indicated by the busy output. busy is low during a conversion. applicatio n s i n for m atio n wu u u the output data is updated at the end of the conversion as busy rises. output data is updated coincident with the rising edge of busy. data will be valid, and can be latched, 20ns after the rising edge of busy. valid data can also be latched with the falling edge of busy or with the rising edge of convst. in the latter two cases the data latched will be for the previous conversion. convst drive considerations timing jitter of the convst signal can adversely affect the noise performance of the ltc1414 when the input signal contains high slew rate components. the falling edge of convst determines the sampling instant. any uncer- tainty in this sampling instant will translate to voltage noise when a fast changing input signal is being sampled. for a full amplitude sinusoidal input, the relationship between timing jitter (t jitter ) and snr j is snr j = 20log(1/2 p ? f in ? t jitter ) where snr j is the signal-to-jitter noise ratio. the internal circuitry of the ltc1414 has been optimized for ultralow jitter (typically 3ps rms). the external clock drive circuitry is equally important and must also have low jitter to achieve low noise. internal clock the internal clock is factory trimmed to achieve a typical conversion time of 330ns and a maximum conversion time over the full operating temperature range of 400ns. no external adjustments are required. the guaranteed maximum acquisition time is 100ns. in addition, a through- put time (acquisition + conversion) of 454ns and a mini- mum sampling rate of 2.2msps is guaranteed. figure 17. timing diagram data (n ?1) db13 to db0 convst busy 1414 f17 t 4 t 5 t conv t 1 t 3 t 2 data n db13 to db0 data (n + 1) db13 to db0 data
19 ltc1414 package descriptio n u dimensions in inches (millimeters) unless otherwise noted. gn package 28-lead plastic ssop narrow (0.150) (ltc dwg # 05-08-1641) 0.386 ?0.393* (9.804 ?9.982) gn28 (ssop) 0398 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 9 10 11 12 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 20 21 22 23 24 25 26 27 28 19 18 17 13 14 16 15 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.0075 ?0.0098 (0.191 ?0.249) 0.053 ?0.069 (1.351 ?1.748) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.009 (0.102 ?0.249) 0.025 (0.635) bsc 0.033 (0.838) ref information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20 ltc1414 ? linear technology corporation 1998 1414fs, sn1414 lt/tp 0399 4k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com typical applicatio u 2.2mhz, 14-bit sampling adc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 f v ref out 2.5v differential analog input ?.5v to 2.5v 10 f 10 f ?v 0.1 f 5v 5v 10 f 14-bit parallel bus ltc1414 a in + a in v ref refcomp agnd d13 (msb) d12 d11 d10 d9 d8 d7 d6 ognd av dd agnd v ss busy convst dgnd dv dd ov dd d0 d1 d2 d3 d4 d5 1414 ta03 related parts part number description comments ltc1412 low power, 12-bit ,3msps, adc nyquist sampling, 150mw, 72db sinad ltc1415 single 5v, 12-bit, 1.25msps, adc single supply, 55mw dissipation ltc1416 low power, 14-bit, 400ksps, adc 5v supplies, 75mw dissipation ltc1417 very low power, 14-bit, 400ksps, adc 20mw, 5v or 5v supply, serial i/o in 16-pin ssop ltc1418 very low power, 14-bit, 200ksps, adc 15mw, 5v or 5v supply, serial or parallel i/o ltc1419 low power, 14-bit, 800ksps, adc true 14-bit linearity, 81.5db sinad, 150mw dissipation ltc1604 high speed, 16-bit, 333ksps, adc 90db sinad, C100db thd, 220mw dissipation lt1460 micropower precision series reference 0.075% accuracy, 10ppm/ c drift

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